Embodiments of the present invention relate to synchronizing serial data which has been transmitted at one rate and recovered at a different rate.
In some data communication arrangements, data are transmitted from one domain at a first rate and received in another domain at a second rate. When the data is recovered, it is normally done N bits at a time. However, the timing differences may sometime cause N+1 or Nxe2x88x921 bits to be recovered. This variation requires some mechanism to establish synchronization at the receiver. In other words, this data coming in at a variable rate must be output at a predictable consistent rate. In the past the necessary elasticity has been provided by using first-in, first-out (FIFO) buffer of sufficient size accommodate variations over the time of a transmitted packet. That is the size is dependent on the maximum number of possible bits of mismatch over the time of a packet. In this arrangement, data was written into the buffer at the transmit rate. When the buffer was half full, read out began at the receive clock rate.
This is a general problem in data transmission where clock rates may vary between the transmitter and receiver. One example, but by no means the only one, is the Universal Serial Bus (USB). The USB is a bus having electrical, mechanical, and communication characteristics that follows a protocol defined in xe2x80x9cUniversal Serial Bus Specificationxe2x80x9d Revision 2.0 published Apr. 27, 2000, by Compaq Computer Corporation, Hewlett-Packard Company, Intel Corporation, Lucent Technologies Inc, Microsoft Corporation, NEC Corporation and Koninklijke Phillips Electronics N.V. The USB Specification provides a standardized approach for component interconnection and data transfer.
From the digital communications perspective, a USB transmitting device sends data in the form of packets over a USB cable to a USB receiving device with the clock signal of the transmitting device being used when encoding digital information. Packets include a defined sync field having multiple bits with a transition for each bit (i.e., from a logic 1 to a logic 0 or vis-versa), a payload with data information, and an end of packet field. The USB Specification does not allow for a separate clock signal to be transmitted and this requires some form of data synchronization.
A similar problem exists when bit stuffing takes place during transmission. For example in a USB transmitter bit stuffing may take place. In that case the bit stuffing defined by the USB specification causes extra bits to be inserted in the transmitted stream. Thus, provision must be made for synchronization between the data source and the transmit circuitry in the presence of these extra bits.
The FIFO elasticity buffer has some problems. It introduces data latency while the buffer is pre-filling and, in the case of the transmitter being faster than the receiver, the buffer is full by the end of the maximum length packet and must be drained before reception of the next packet can begin. Furthermore, a FIFO which operates at the data rates currently needed, e.g., 480 Mb/s is not easy to implement in readily available CMOS ASIC library elements
A need, therefore, exists for a technique of transferring signals between multiple clock timing domains that reduces or addresses these problems.